IBM and Samsung claim they’ve made a breakthrough in semiconductor design. On day one of the IEDM conference in San Francisco, the two companies unveiled a new design for stacking transistors vertically on a chip. With current processors and SoCs, transistors lie flat on the surface of the silicon, and then electric current flows from side-to-side. By contrast, Vertical Transport Field Effect Transistors (VTFET) sit perpendicular to one another and current flows vertically.
According to IBM and Samsung, this design has two advantages. First, it will allow them to bypass many performance limitations to extend Moore’s Law beyond IBM’s current nanosheet technology. More importantly, the design leads to less wasted energy thanks to greater current flow. They estimate VTFET will lead to processors that are either twice as fast or use 85 percent less power than chips designed with FinFET transistors. IBM and Samsung claim the process may one day allow for phones that go a full week on a single charge. They say it could also make certain energy-intensive tasks, including cryptomining, more power-efficient and therefore less impactful on the environment.
IBM and Samsung haven’t said when they plan to commercialize the design. They’re not the only companies attempting to push beyond the 1-nanometer barrier. In July, Intel said it aims to finalize the design for angstrom-scale chips by 2024. The company plans to accomplish the feat using its new “Intel 20A” node and RibbonFET transistors.
Update 12/12 12:20PM ET: IBM has clarified that VTFET will help it expand beyond its existing nanosheet technology, not necessarily to chips denser than 1nm. It also noted that you can have extreme improvements in performance or battery life, but not both. We’ve updated the article accordingly and apologize for the error.